New IEEE Computer Article features Work at Lawrence Berkely Labs

See the article in the Nov. issue of Computer titled "Energy-Efficient Computing for Extreme-Scale Science" by CTO Chris Rowen and others about the work on low-power design at Lawrence Berkeley Labs. http://www.tensilica.com/uploads/pdf/ieee_computer_nov09.pdf

Everything You Know about Microprocessors is Wrong

Here's a great web seminar that's archived, so you can view it any time. Many system-engineering concepts and "best practices" with respect to system design are no longer valid at the chip level. For example, bus-centric design--made popular by the introduction of the first commercial microprocessor in 1971--continues to dominate on-chip design 36 years later even though nanometer silicon has completely changed the rules of system interconnect.

Xtensa 8 and LX3 are out - it's time to party

Today we have a company-wide bowling tournament offsite to celebrate the release of our eight generation processors - Xtensa 8 and Xtensa LX3. Fun for all!

What's the fastest route from C algorithm to gates?

You've got an algorithm written in C. You can quickly see how that will run on a standard processor core, but you'd be amazed how much faster that algorithm can run on a specially tailored processor. A simple example is an audio stream. If the datapath of a processor is specially tailored just for audio data, that's going to go through the processor much faster, and therefore better quality sound. The same holds true for other data-intensive applications, especially when the datapath doesn't exactly fit into 32 bit words. Find out more from this white paper: http://www.tensilica.com/products/literature-docs/white-papers/fast-path-from-c-to-gates/

Xtensa 8 or Xtensa LX3?

Xtensa LX3 is a superset of Xtensa 8 and adds some very powerful features. Find out more at http://www.tensilica.com/products/xtensa-customizable/xtensa_choice.htm

Grant Martin at Synopsys Interoperabity Forum Tomorrow 1:15 in Santa Clara

See our Chief Scientist talk in the System-level design section - topic: Getting high with a little help from my friends: Configurable processor interoperability with ESL tools.

Xtensa LX3 - 10 GigaMAC/Sec DSP Performance, tops 1 GHz

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm² and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm² (post place-and-route 45GS) and consuming just 170 mW (including leakage).

Grant Martin in Tutorial at ICCAD 4:30 today

Embedded Processors, Methods and Applications: Computer Architects Perspective

As feature sizes diminish and transistors multiply, designers are compelled to move to higher levels of abstraction to overcome the productivity gap. Increasingly designers use processors as the main module in embedded system design. The available choices to the modern designer include processor (which are both non-configurable and configurable), DSP and GPU cores. This tutorial explores the available processors, details methodologies and explains applications.

The tutorial is divided into three parts: the first will explore the field of embedded processors; the second will look design methodologies based on embedded processors; the third, will describe an application in detail. This tutorial will be presented by three experienced researchers with industrial and academic experience, and will benefit students, researchers, and design engineers.

Speakers:

Grant Martin - Tensilica, Inc.
Sri Parameswaran - Univ. of New South Wales
Anand Raghunathan - Purdue Univ.
http://www.iccad.com/events/eventdetails.aspx?id=106-3-E

Sign up for our Web Seminar: The 5 Pitfalls of 4G Baseband Design

Sign up now for our web seminar next Tuesday, October 27, at 11 am pacific daily time. It will be recorded, so you can watch it later, too. Chris Rowen, our CTO, will talk about the emerging LTE standard, which is complex, requires extraordinary computation throughput and much better power efficiency than previous wireless baseband PHY subsystems. Because of the complexity, designers are taking many different approaches to chip design for LTE.

This webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE's many modes, excessive cost and power, the "million MIPS" hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. This webinar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don'ts. http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=tensilica_oct2709

More Configuration Optons Than Ever in Xtensa 8

Want your processor core your way but don't want to work hard at it? Just look at all of the configuration options you get with Xtensa 8. Just click on a button or use a pull-down menu to make your selections - then you can get your processor you way. See http://www.tensilica.com/products/xtensa-customizable/xtensa/configurability.htm