Xtensa 8 - Our 8th Generation Processor with Novel I/O

By embedding functionality right into the processor datapath itself, designers can use the Xtensa 8 DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs. See http://www.tensilica.com/products/xtensa-customizable/xtensa.htm